Flexible and Transparent Artificial Synapse Devices Based on Thin-Film Transistors with Nanometer Thickness

Introduction

In recent years, amorphous oxide semiconductor (AOS) devices have attracted much attention. A representative AOS material is In-Ga-Zn-O (IGZO) which has been one of the most popular AOS materials since it was first published in 2004.¹ They have some attractive properties, including transparency, flexibility, relatively low-cost fabrication and low-temperature processing at no higher than 200 °C. TFTs can be used as pressure and temperature sensors.^2,3 TFTs are used in many ways and artificial synapse devices based on TFTs have been extensively studied, however, flexible and transparent artificial synapses based on nano TFTs have not been researched as much despite their promise in numerous applications. Synapse is the functional unit in the brain, and it connects the presynaptic and postsynaptic neurons.⁴ In biological synapses, action potentials reach the pre-synapse, promote the release of the neurotransmitter, and cause excitatory postsynaptic potential (EPSP).⁵ In the artificial synaptic device mentioned in the manuscript, a voltage is applied to the gate electrode to simulate the action potential, and the change of the channel current is to simulate the excitatory postsynaptic current. Therefore, the presynaptic stimulation is the pulse applied to the gate electrode.^6,7

For example, neurosynaptic behaviors are the basis of our learning, memory, and information processing. Artificial synaptic devices based on flexible TFTs can mimic biological synaptic behaviors like our brain and be useful for a number of applications.⁸ Therefore, artificial synapse devices are worthy of further study. The biological synapse-like behaviors include information memory and possessing, which are triggered by the inflow dynamics of ion transport. Artificial flexible organic synaptic transistors capable of concurrently exhibiting signal transmission and learning functions were verified using a C₆₀/poly (methyl methacrylate) (PMMA) hybrid layer.⁹ Photonic non-volatile memory devices with hybrid polymer/UC nanocrystal composite materials as the active layer have been confirmed.¹⁰

In this work, the flexible and transparent artificial synapse devices based on TFTs with PET as the flexible substrate, ITO as the gate, and PVA as the gate insulation layer were made and showed some representative synaptic characteristics. The device shows good synaptic plasticity. Some biological synapse-like behaviors are mimicked in this paper, for instance, excitatory postsynaptic current (EPSC),^11–13 paired-pulse facilitation (PPF) and long-term memory (LTM) demonstrating much promise for these materials in many fields.^14–17 As far as we know, few previous publications are on such a standard thin-film transistor structure, which is based on PVA insulators and IGZO semiconductors. At the same time, the design here has a combination of artificial synapse functions and temperature sensor characteristics.

Materials and Methods

As shown in Figure 1A and B, the bottom-gate top-contact structure was used for the design of the present flexible and transparent TFTs. The TFTs employed PET as the flexible substrate, ITO as the bottom gate, and PVA as the gate insulation layer. For the deposition of the gate insulation layer, the processing steps were as follows. First, a 10 wt% PVA solution was prepared by magnetic stirring and heating in ambient air. The solution used for the spin-coating of the PVA insulator layer was deionized water. PVA acted as the insulating layer on the ITO gate and was added via a spin coating method at a speed of 200 rpm for 3 s and 2000 rpm for 20 s. Afterward, it was heated at 90 °C for 30 minutes. The IGZO films acted as the semiconductor layer with a thickness of 35 nm or so and were deposited on the insulating layer by radio-frequency (RF) magnetron sputtering. The RF magnetron sputtering instrument was produced by Shenyang Scientific Instrument Co., Ltd., Chinese Academy of Sciences. The IGZO films were formed by using an IGZO target and a shadow mask (size: 600 μm × 800 μm). The composition of the IGZO sputtering target was the molecular ratio of In₂O₃: Ga₂O₃: ZnO = 1: 1: 1. The deposition conditions included an RF power of 100 W, a pressure of 0.5 Pa, Ar gas flow rate of 14 sccm and sputtering time of 5 min. In Figure 1C and D, for the source and drain electrodes, a ~100 nm-thick top ITO electrode layer was deposited on the IGZO channel layer and formed a covering in contact with the IGZO channel layer. The deposition conditions were the same as IGZO except the sputtering time was about 15 min. The source and drain electrodes could also be deposited by RF magnetron sputtering with a shadow mask (size: 150 μm × 1000 μm). Figure 1C is the SEM image, obtained from FEI Quanta 250 FEG produced by Keesida Co., LTD. The artificial synapse behavior of the devices was measured and investigated using a Keithley 4200 semiconductor analyzer.

Figure 1 Thin-film transistor-based synapse device. (A) Three-dimensional structure of the single thin film transistor. (B) Cross-section structure of the single thin film transistor. (C) SEM top image of a single device and (D) Flexible transparent single device in an enlarged image.

Results and Discussion

Figure 2A shows the transfer characteristic curve, where V_DS is 1.1 V, the gate voltage V_GS is scanned from 2 V to 3 V, and the voltage sweeping rate is 0.1 V. It can be calculated that I_ON/I_OFF = 4.58×10⁶ from the data in Figure 2A. The carrier charges gradually increase on the interface between the dielectrics and IGZO semiconductor channel as the voltage increases, and then the current is generated between the source and the drain electrodes. As shown in the Figure 2B, the V_DS sweeps from 0 V to 2 V, and the gate voltage V_GS increases from 0.35 V to 2 V with a step of 0.55 V. When V_DS is consistent, the value of I_DS increases when V_GS increases, so the black line at the bottom represents V_GS = 0.35 V. As can be seen from the figure, when the V_DS is low, the device has an obvious linear region. When the V_DS is high, the device shows good saturation current characteristics. The device can be used as temperature sensors, too. In Figure 2C, the transfer curves are measured when the drain-source voltage V_DS = 1 V. When the temperature increases, the curves have a positive shift, this is the key to prove the device can work as a temperature sensor. The continuous modulation of the synaptic weight can be defined as synaptic plasticity.¹⁸ Therefore, the synapse can perform learning and memory functions. Spiking-rate dependent plasticity (SRDP) belongs to the class of synaptic plasticity. It is important to realize this in artificial synapses. Figure 2D shows the experiment of the spiking-rate dependent plasticity (SRDP). The drain-source voltage is 1.5 V and the gate-source voltage is 2 V. Here, the pulse width and pulse interval remain the same. When the pulse interval is 0.02 s, 0.03 s, and 0.04 s, the corresponding amplitudes of the drain current are 12 µA, 8 µA, and 6 µA, respectively, which decrease sequentially. The synaptic response is related to the frequency and can prove the learning rule of SRDP. Due to the change of the frequency, the synapse weight between neurons changes. In other words, presynaptic spikes with high frequency will lead to potentiation, whereas presynaptic spikes with low frequency will result in depression.

Figure 2 The biological synapse-like transfer and output characteristic curves of the thin film transistors (TFTs). (A) Transfer characteristic curves. (B) Output characteristic curves. (C) Transfer curves measured by different temperatures and (D) The spiking-rate-dependent plasticity experiment.

Figure 3A shows a simplified biological dendritic synapse. A synapse is a connection between two neurons in the brain which allow neurons to transmit electrical or chemical signals to another neuron.¹⁹ The local magnification shows that synaptic plasticity is regulated by the migration of neurotransmitters, which are triggered by ion exchange at the membrane and synaptic junctions when the stimulation signal arrives.^20,21 When the nerve impulse reaches the presynaptic region, the voltage-gated ion channel is opened, and then the ions migrate through the channel, causing the neurotransmitter to release into the synaptic spaces. The neurotransmitters then bind to the postsynaptic receptors to complete transmission of the information. Therefore, the ion transport plays a key role in regulating synaptic weight and transport information. As shown in Figure 3B, the gate electrode of the flexible and transparent TFTs corresponds to the presynaptic region, the source/drain electrode as the postsynaptic region, the IGZO channel as the synaptic cleft, and the carriers in the channel as the ions in the neural synapse.

Figure 3 (A) Structure of synapses, including the synaptic cleft; presynaptic and postsynaptic neuron parts and (B) Corresponding relationship between biological synapses and TFTs.

Figure 4A shows the measurement condition for the Keithley 4200 with probe pulses. One or more pulses are applied to the gate electrode and then the current at the drain is read. Figure 4B shows the EPSC of the artificial synaptic transistor and during the EPSC measurement, a constant drain voltage of 1.5 V was applied. The EPSC was triggered by a presynaptic spike (9.0 V, 1.0 s) on the ITO bottom gate electrode. The presynaptic spike triggers an EPSC current with a peak value of ~2.5×10⁻⁶ A and at the end of the spike, it gradually reduced to the initial current. When the voltage increases and the transistor is in the over-threshold region, the channel can be seen as a capacitor. Voltage pulses with amplitudes 915 V can be regarded as the maximum voltage at which the capacitor discharges. When a positive presynaptic spike is applied on the bottom ITO gate electrode, the mobile carriers will migrate and accumulate at the interface between the dielectrics and the IGZO semiconductor channel. When the spike ends for a while, the accumulated carriers will gradually migrate back to their initial equilibrium position due to the concentration gradient.²² The postsynaptic parameters can influence the EPSC, and it can be found in our previous publications.¹¹ The drain-source voltages can provide a range of post-spikes and influence the output current. The equation can be seen as follows:

(1)

where τ is the retention time, t₀ is the time when the presynaptic spike finishes, I₀ is the triggered maximum EPSC, and I_∞ is the EPSC at the end of the presynaptic spike. τ is found to be voltage-dependent.

When the presynaptic neurons are stimulated by two consecutive pulses, the second peak triggered by the pulses is larger than the first peak. This phenomenon is called a paired-pulse boost (PPF), which plays an important role in visual and auditory signal processing.²³ Here, we can imitate the phenomenon of the PPF in the artificial synaptic transistor. Figure 4C shows a PPF response in the flexible and transparent artificial synaptic transistor. Two successive identical pulses (15.0 V, 1.0 s) with an interval time of 2.8 s are applied to the ITO gate with a constant V_D of 1.5 V. The values of the first EPSC (I₁) and the second EPSC (I₂) are respectively ~6.9×10⁻⁷ A and ~4.5×10⁻⁶ A, meanwhile, an EPSC gain (I₂/I₁) of ~6.5 times is obtained. At the end of the first spike, some of the activated carriers remain on the interface between the IGZO channel and the insulating layer before they return to their original position.¹⁷ Therefore, when the second peak is applied to the gate after the first spike with a small inter-spike interval, the values of the second EPSC (I₂) is larger than the first EPSC (I₁).

In the biological nervous system, some of the changes in synaptic connections can last for hours or even days. This phenomenon is known as the long-term memory (LTM), which is the basis for learning, memory and information processing.²⁴ As shown in Figure 4D, ten sequential identical pulses (15.0 V, 1.0 s) with an interval time of 2.0 s are applied to the ITO gate with a constant V_D of 1.5 V. Figure 4C shows the peaks progressively increase by the successive application of gate pulses and it lasts a long time after the end of the pulse. The LTM process is due to some of the carriers of the IGZO channel changing irreversibly under the continuous high gate pulses.²⁵

Figure 4 (A) The pulse measurement schematic diagram based on IGZO transistors. (B) The excitatory postsynaptic current (EPSC) plotted versus time. (C) A PPF response for the artificial synaptic transistor and (D) The EPSC response triggered by ten sequential gate pulses.

Artificial synaptic behaviors are caused by charging and discharging of the moving carriers stimulated by the gate pulse as shown in Figure 5. Figure 5A shows that the carrier transport behavior during a period of the pulse could be divided into five stages: the basic voltage V₁, the instantaneous rising voltage V₂, the higher voltage V₃, one instantaneous dropping voltage V_4, and the last basic voltage V₅. As shown in Figure 5B, at stage ①, when the V₁ is applied, the mobile carriers are not attracted to the interface between the dielectrics and the IGZO semiconductor channel. At stage ②, when the V₂ is applied to the gate, it increases instantaneously, and the mobile carriers at the interface between the IGZO channel and the insulating layer PVA gradually increase. Meanwhile, the functional groups such as In-O, Ga-O, and Zn-O can interact with metal ions and persist in the channel. At stage ③, when the gate voltage is kept at a higher voltage V₃, more carriers remain at the interface between the dielectrics and the IGZO semiconductor channel. Stage ④ is just the opposite of stage ②. The accumulated mobile carriers at the interface between the dielectrics and the IGZO semiconductor channel are driven back into the source and the drain electrodes. The migration rate in stage ④ is slower than in stage ②, because, at stage ②, the free carriers move faster under pulse pressure, while at stage ④, free carriers diffuse slower back to the original position due to the concentration gradient.²⁶ Stage ⑤ is the same as stage ①. When the gate voltage drops to V₅, there are no carriers at the interface between the IGZO channel and the insulating layer and then the device returns to its initial state.^27,28

Figure 5 (A) Schematic diagram of the pre-synaptic spike applied to the gate electrode and (B) Overview of the voltage pulse profile and the corresponding discharge current in the TFTs with the IGZO channel.

Conclusion

In summary, in this study, we have fabricated flexible and transparent artificial synapse transistors with PET as the flexible substrate and PVA as the dielectric layer, and its I_ON/I_OFF ratio was 4.58×10⁶. The TFTs have a thickness on the order of nanometers. They can be used as temperature sensors and shows good spiking-rate dependent plasticity (SRDP). Furthermore, we succeeded in mimicking the biological synapse-like behaviors of EPSC, PPI, and LTM in the biological nervous system with artificial synaptic transistors. Although it cannot be used on a large scale at present, such artificial synaptic transistors provide a possibility to realize synaptic-like information processing and learning, and lay the foundation for the development of artificial intelligence.